`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:24:17 12/02/2020 
// Design Name: 
// Module Name:    TDecoder 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
include "defines.v";

module TDecoder(
    input [31:0]instruction,
	 output MD,
    output reg [4:0] useAddress1,
    output reg [2:0] Tuse1,
    output reg [4:0] useAddress2,
    output reg [2:0] Tuse2,
	 output reg [4:0] newAddress,
    output reg [2:0] Tnew
    );
	assign MD = (MULT || MULTU || DIV || DIVU || MFHI || MFLO || MTHI || MTLO);
	wire [4:0]rs, rt, rd;
	wire [5:0]opCode,func;
	 instructionSplitter splitter(
		.instruction(instruction),
		.rs(rs),
		.rt(rt),
		.rd(rd),
		.opCode(opCode),
		.func(func)
	 );
	wire 	LB,LBU,LH,LHU,LW,SB,SH,SW,ADD,ADDU,
		SUB, SUBU, MULT, MULTU, DIV, DIVU, SLL, SRL, SRA, SLLV,
		SRLV,SRAV,AND,OR,XOR,NOR,ADDI,ADDIU,ANDI,ORI,
		XORI,LUI,SLT,SLTI,SLTIU,SLTU,BEQ,BNE,BLEZ,BGTZ,
		BLTZ,BGEZ,J,JAL,JALR,JR,MFHI,MFLO,MTHI,MTLO;
assign LB = `LB;
assign LBU = `LBU;
assign LH = `LH;
assign LHU = `LHU;
assign LW = `LW;
assign SB = `SB;
assign SH = `SH;
assign SW = `SW;
assign ADD = `ADD;
assign ADDU = `ADDU;
assign SUB = `SUB;
assign  SUBU = ` SUBU;
assign  MULT = ` MULT;
assign  MULTU = ` MULTU;
assign  DIV = ` DIV;
assign  DIVU = ` DIVU;
assign  SLL = ` SLL;
assign  SRL = ` SRL;
assign  SRA = ` SRA;
assign  SLLV = ` SLLV;
assign SRLV = `SRLV;
assign SRAV = `SRAV;
assign AND = `AND;
assign OR = `OR;
assign XOR = `XOR;
assign NOR = `NOR;
assign ADDI = `ADDI;
assign ADDIU = `ADDIU;
assign ANDI = `ANDI;
assign ORI = `ORI;
assign XORI = `XORI;
assign LUI = `LUI;
assign SLT = `SLT;
assign SLTI = `SLTI;
assign SLTIU = `SLTIU;
assign SLTU = `SLTU;
assign BEQ = `BEQ;
assign BNE = `BNE;
assign BLEZ = `BLEZ;
assign BGTZ = `BGTZ;
assign BLTZ = `BLTZ;
assign BGEZ = `BGEZ;
assign J = `J;
assign JAL = `JAL;
assign JALR = `JALR;
assign JR = `JR;
assign MFHI = `MFHI;
assign MFLO = `MFLO;
assign MTHI = `MTHI;
assign MTLO = `MTLO;
 
	always @*
	begin
		if(SB || SH || SW)
		begin
			useAddress1 <= rs;
			Tuse1 <= 1;
			useAddress2 <= rt;
			Tuse2 <= 2;
			newAddress <= 0;
			Tnew <= 0;
		end


		else if(LB || LBU || LH || LHU || LW)
		begin
			useAddress1 <= rs;
			Tuse1 <= 1;
			useAddress2 <= 0;
			Tuse2 <= `notUse;
			newAddress <= rt;
			Tnew <= 2;
		end


		else if(SUB || SUBU || ADD || ADDU || AND || OR || XOR || NOR || SLT || SLTU || SLLV || SRLV || SRAV)
		begin
			useAddress1 <= rs;
			Tuse1 <= 1;
			useAddress2 <= rt;
			Tuse2 <= 1;
			newAddress <= rd;
			Tnew <= 1;
		end
		
		else if(SLL || SRL || SRA)
		begin
			useAddress1 <= rt;
			Tuse1 <= 1;
			useAddress2 <= 0;
			Tuse2 <= `notUse;
			newAddress <= rd;
			Tnew <= 1;
		end

		else if(ADDI || ADDIU || ANDI || ORI || XORI || LUI || SLTI || SLTIU)
		begin
			useAddress1 <= rs;
			Tuse1 <= 1;
			useAddress2 <= 0;
			Tuse2 <= `notUse;
			newAddress <= rt;
			Tnew <= 1;
		end


		else if(BEQ || BNE)
		begin
			useAddress1 <= rs;
			Tuse1 <= 0;
			useAddress2 <= rt;
			Tuse2 <= 0;
			newAddress <= 0;
			Tnew <= 0;
		end


		else if(BLEZ || BGTZ || BLTZ || BGEZ)
		begin
			useAddress1 <= rs;
			Tuse1 <= 0;
			useAddress2 <= 0;
			Tuse2 <= `notUse;
			newAddress <= 0;
			Tnew <= 0;
		end


		else if(MULT || MULTU || DIV || DIVU)
		begin
			useAddress1 <= rs;
			Tuse1 <= 1;
			useAddress2 <= rt;
			Tuse2 <= 1;
			newAddress <= 0;
			Tnew <= 0;
		end


		else if(MFHI || MFLO )
		begin
			useAddress1 <= 0;
			Tuse1 <= `notUse;
			useAddress2 <= 0;
			Tuse2 <= `notUse;
			newAddress <= rd;
			Tnew <= 1;
		end
		
		else if(MTHI || MTLO)
		begin
			useAddress1 <= rs;
			Tuse1 <= 1;
			useAddress2 <= 0;
			Tuse2 <= `notUse;
			newAddress <= 0;
			Tnew <= 0;
		end
		else if(J)
		begin
			useAddress1 <= rs;
			Tuse1 <= 0;
			useAddress2 <= 0;
			Tuse2 <= `notUse;
			newAddress <= 0;
			Tnew <= 0;
		end
		
		else if(JR)
		begin
			useAddress1 <= rs;
			Tuse1 <= 0;
			useAddress2 <= 0;
			Tuse2 <= `notUse;
			newAddress <= 0;
			Tnew <= 0;
		end


		else if(JALR)
		begin
			useAddress1 <= rs;
			Tuse1 <= 0;
			useAddress2 <= 0;
			Tuse2 <= `notUse;
			newAddress <= rd;
			Tnew <= 1;
		end


		else if(JAL)
		begin
			useAddress1 <= 0;
			Tuse1 <= 0;
			useAddress2 <= 0;
			Tuse2 <= `notUse;
			newAddress <= 31;
			Tnew <= 1;
		end


	end
	
endmodule
